Society For Electronic Transactions And Security Recruitment 2019 For Research Associate/ Jrf Engineering

Society For Electronic Transactions And Security - Experience : Freshers

Society for Electronic Transactions and Security recruitment for 2019 for research associate/ jrf engineering in chennai. Apply for research associate/ jrf engineering govt job in society for electronic transactions and security.
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Job Title : Research Associate/ JRF Engineering
Company Name : Society For Electronic Transactions And Security
Job Location : Chennai , Tamil Nadu
Education : M.E. / M.Tech ,M.Phil
Category : Government Jobs
Experience : Freshers
Post Date : 15 May, 2019
Last Date : 15 June, 2019
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Job Details

Research Associate/ JRF  Engineering job opportunities in Society for Electronic Transactions and Security (SETS)

Title of the Sponsored Project: Design and Development of Fast and Robust Authentication and Key Distillation Protocols for QKD systems

Post 1: Research Associate/ Number of Posts: 1

Essential Qualifications:
a) Ph.D in Engineering/Science in the relevant area of the project or b) M.E/M.Tech in Microelectronics and Photonics/ Laser and Electro Optics/ Electronics and Communication Engineering/ VLSI Design/ Digital Electronics/ Embedded Systems/ or equivalent from a recognized university with First Class or equivalent with at least 3 years of relevant experience. 

Desirable Skills/ Knowledge: a) Knowledge of Quantum Communication and Information. 

b) Hands-on experience in optical communication interfaces. 
c) Knowledge of Xilinx FPGA implementation flow and tools.
d) Knowledge of FPGA realization and control softwares.

Salary: Rs 47000 p.m. plus 24% HRA 
Selection Procedure: Interview 

Post 2: JRF / Number of Posts: 2

Essential Qualifications: M.E/M.Tech in Electronics and Communication Engineering/ Digital Electronics/Embedded Systems/VLSI Design/ Microelectronics and Photonics/ Laser and Electro Optics/ or equivalent from a recognized university with First Class or equivalent.

Areas of Skill sets/ Knowledge required:
a) Knowledge of Xilinx FPGA implementation flow and tools 
b) Hands-on experience in simulation using MATLAB/ModelSim and FPGA realization using VHDL/Verilog programming. 
c) Knowledge of clock, memory, DCM, and I/O management and implementation on FPGAs (desirable) d) Experience in design integration, FPGA I/O communications and testing (desirable)

Selection Procedure: Written Test and Interview Increment: The positions as proposed are purely temporary on Contract basis with consolidated salary under the project.

The contract will be for 3 years. In each year, performance review shall be made to ensure continuation.
Upon satisfactory performance, RA will be paid Rs 49000 p.m. plus 24% HRA for the 2 nd year and Rs 54000 p.m. plus 24% HRA for the 3rd year.

The JRF will become SRF after two years and will be paid Rs 35000 p.m. plus 24% HRA for the 3rd year. Other rules apply as per prevailing DST norms.
 

Candidate Profile

ME/M.Tech, M Phil / Ph.D

Education : M.E. / M.Tech ,M.Phil

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About Society For Electronic Transactions And Security
Research Associate/ JRF Engineering Jobs in Society For Electronic Transactions And Security
SETS is an initiative of the Central Government through the Office of the Principal Scientific Adviser (PSA) to the Government of India. SETS was set up for the purpose of nucleating, sensitising and developing technologies that can protect the information wealth of the country. Such an idea to form a specialized organisation in the area of information security was conceived by Dr. A.P.J. Abdul Kalam, formerly the Honble President of India and was implemented by Dr. R.Chidambaram from the Office of the PSA.
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