Sasken Interview
It was one and hour paper. It has got three sections. Total Marks 60
1.Multiple Choices.
2.TRUE and False.
3.Descriptive
Following are section 1 and section2 questions.
1.How Jk F/F can be converted into T F/F.
2.Difference between display and write in Verilog.?
3.ASIC flow steps? (RTL design ->Functional Verification->Synthesis ->STA->Place and route)
4.Difference between Latch and F/F?Which is faster?
5.Difference/Comparison between DRAM and SRAM?
6.what happens to Vth if temp Increases>?
7.In a negative feedback control System ,If feed factor Increases what happens to Gain and Bandwidth?
8.NMOS and PMOS will pass which value without degradation?[NMOS -0 and PMOS -1]
9.AB+B�C
(i).Cant be further reducible and glitch
(ii)Can reducible further and cant glitch
10.which is faster :read cache or write cache?
11.Noise Margin Definition?
12.What happens to power If Vth increases In CMOS?
13.enum = {a=1,b=5,c,d}
What is the c and d?
14(.A�+B�) is equivalent to?
15.How can we Increase the slope of Trasnfer chacteristics of a CMOS?
(i)Increasing W/L ratio of PMOS and NMOS In the same proportion
(ii) Increasing W/L ratio of PMOS and NMOS In different proportion
(iii) Increasing W/L ratio of PMOS only
(iv) Increasing W/L ratio of NMOS only
Descriptive Questions
1.What happens If we interchange PMOS and NMOS in a CMOS Inverter?
2.Why PMOS width should be greater than NMOS?
3.int a =0;
If(a++) print (�Example1�);
else if (++a) print (�example2);
(i)What is the output if the program?
(ii)What is the value of i?
4.What are the advantages and disadvantages of Pipeline operation?
5.Draw the output waveform?
(i) initial begin
Y = #5 0;
Y = #3 1;
Y = # 8 0;
(ii) Y
