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Some Sample questions (m.tech.) tech.--24, apti.--20
On cmos power( formula- P=CV*Vf
Lowest noise margin in which logic family--
a) TTL b) CMOS c) biCMOS d) all have same
If CMOS has tr(rise time)=tf.find Wp/Wn. given beta(n)=2*beta(p)
gm of a transistor is proportional to
a)Ic b)Vt c)1/Vt d)none
If A and B are given in 2,s complement find A-B in decimal.
Set up time,hold time ,clock to Q delay time (very important)
.3 questions on opamp (transfer function)(2 marks each)
2 questions on sequence detector (2 marks each)
Logic function boolean expressions(true/false) (3 question-1 mark each)probabily all false
In I/O mapped how do you represent memory(1 mark)
The design of FSM(finite state machine) will--
a) increase time of design
b) increase delay
c) increase power
d) all of the above
K-map minimization
Phase locked loop(PLL) 1 question sachin
