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Rtl Verification Jobs

Shell Info Technologies Private Limited
Job Description
JD for RTL Verification:
Location:-Bangalore/Noida
Exp: - 5+ yrs.

DV - Design Verification: -
SCOPE: Individual Contributor - Responsible for participating in ASIC and FPGA implementation and verification for the Design Services organization
JOB SUMMARY:
The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.
The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilogs Universal Verification Methodology (UVM) is preferred.
ESSENTIAL FUNCTIONS:
o Basic understanding of CMOS ASIC fundamentals
o Knowledge of all phases of ASIC design and test methodology
o Basic understanding of Timing Analysis
o Verilog / VHDL
o Linux/Unix environment
o Team Player
o Good Communication Skills
Desired Capabilities
o Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
o Knowledge of System Verilog
o Knowledge of UVM
o FPGA based designs
o Test Planning & Verification
EXPERIENCE AND EDUCATION:
o A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
o Minimum of 5 years experience with standard cell ASIC and / FPGA design.
o Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.
o Demonstrated ability designing independently for medium/high complexity problems.
oStrong oral and written communication skills in English and ability to present technical information.

Qualification: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics


Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Software - Embedded, EDA, VLSI, ASIC, Chip Design
Role Category: Programming & Design
Role: Testing Engineer
Employment Type: Permanent Job, Full Time
Keyskills:
System VerilogAxiAhbUVMVHDLRtl VerificationCFPGA DesignDesign VerificationASIC Design
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Qualities Needed for This Jobs
System Verilog, Axi, Ahb, Uvm, Vhdl, Rtl Verification, C, Fpga Design, Design Verification, Asic Design
Candidate Profile
Jd For Rtl Verification:location:-bangalore/noidaexp: - 5+ Yrs.dv - Design Verification: -scope: Individual Contributor - Responsible For Participating In Asic And Fpga Implementation And Verification For The Design Services Organizationjob Sum
Looking for B.e/b.tech,m.e/m.tech/ms graduates profile.
2018-11-07 to 2019-01-06
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More Information
Location Noida,bengaluru / Bangalore
Education B.e/b.tech,m.e/m.tech/ms
Experience 5 (yrs)
Industry Human Resources
Job Type : Full-time
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