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Neugene International Solutions
Job Shared by MonsterIndia
Job Description
(8+ Yrs of experience in DFT with 3+ Yrs in leading the SoC level DFT implementation)
- Should have experience in leading the SoC level implementation (hierarchical) for Scan, MBIST, BSCAN insertion
- Experience in Mentor Graphics tools/flows preferred TestKompress , Tensest/LV MBIST, Mentor TAP Generation
- Understanding of EDT generation, implementation flow, OCC structure definitions for partitions and full-chip level and integration across
- Interface between Design and PD and driving implementation as per Full-chip level DFT spec from the DFT architect on Scan, MBIST and BSCAN
Qualities Needed for This Jobs
Dft Engineer, Dft Implementation, Mbist, Bscan, Tap Generation, Rtl-glue, Muxing, Chip Level, Chip Design, Chip Architecture, Testkompress, Edt Generation, Full Chip Level Integration
Candidate Profile
8+ Yrs Of Experience In Dft With 3+ Yrs In Leading The Soc Level Dft Implementation
Looking for B.e/,m.e/ graduates profile.
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More Information
Location Mumbai
Education B.e/,m.e/
Experience 8 (yrs)
Industry Computers / IT
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