JOB DESCRIPTION:Roles and Responsibilities:The individual will be responsible for the qualification of the FPGA Synthesis productsThe individual will be responsible for validating new features being developed for Mentor FPGA Synthesis products by creating new designs using HDL languages (VHDL, System Verilog). It also includes developing test plans, execution and maintaining regression harness. The individual will be responsible for replicating Mentor FPGA Synthesis customer use models in internal verification flows, and interacting with customers as needed The individual will be responsible for creating design flows for benchmarking against vendor tools for QoR, Area, Power.The individual will work on verticals of FPGA synthesis like ASIC Prototyping, Formal Verification flows etc.The individual will work closely with the software application developers and product marketing team to help deliver timely product releases that effectively meet our customer's needs. Required Skills:Should have good knowledge on FPGA/ASIC design flowsGood knowledge of FPGA tools like (ISE/VIVADO/Quartus.) and synthesis tools Precision and SynplifyExpertise in RTL HDLs (Verilog, VHDL, System Verilog) and FPGA device architecture Scripting knowledge (Perl/shell/python/) Hands on LINUX knowledgeDesirable Skills:Formal verification flow experienceASIC prototyping experienceFPGA validation flows including lab debug experience with Chipscope and Signal Tap will be plus.B.Tech/M.Tech in ECE/EE from reputed engineering collegeExperience (5-8 years)
Qualities Needed for This Jobs
Rtl Design, Rtl Coding, Rtl, Ip Design, Rtl Ip, Ip Rtl, Intellectual Property, Fpga, Asic Fpga, Fpga Asic, Logic Design, Logic-design
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