Verification Engineer Job DescriptionResponsible for the development of leading edge verification methodologies for complex Mixed Signal ICs.Duties:- Design and implement a UVM based verification infrastructure and test cases for system, chip and block level verification, using SystemVerilog. Implement Pseudo-random and functional coverage verification methodologies Develop functional test and verification plans. Work closely with the IC design team to plan and implement design verification strategies.Required Skills and Experience BS in Electrical Engineering, Computer Science or equivalent 8years experience Strong working knowledge of SystemVerilog and UVM Experience writing models in a UVM environment Must be proficient in Pseudo-random and functional coverage verification methodologies Preferably some experience with formal model checking tools such as Cadence IFV Preferably some experience with Signal Conditioning or ADC chips Good communication skills
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