Intel India Development Center focuses on creating innovative products that advance the next generation of technology. Intel with its strong technology heritage, provides an opportunity to work on cutting-edge technology, pushing the boundaries of innovation and transforming the way people live and work.
Job Description
Intel's ASDG HIP (Atom and Soc Development Group) is chartered with defining modular IP standards for SoC architecture, test/validation, and for providing re-useable hard and soft IP blocks for use within multiple SoC product groups. This is part of the SoC Mega-Initiative across Intel. ASDG HIP India is a key site from DDR, Display Port, LVDS, Memory Compiler, VR IP Development for ASDG global. ASDG HIP India is a multifunctional team consists of Circuit Design, Mask Design, Electrical Validation skills.
Job Scope
o Analog and mixed-signal Circuit Design, simulation, Verification in CMOS Technology
Desired Profile
o Understanding of the silicon development and validation cycle, CAD Tools
o Strong Analytical, problem-solving and debug skills
o Good teamwork skills, and strong verbal and written communication skills
Qualifications
The candidate should possess a Bachelor or Master of Engineering degree, or a Master of Science degree in Electrical or Electronics and Communication Engineering with 0-2 years of relevant work experience. The candidate should also have:
o In-depth and hands-on expertise in circuit and High speed IO design and pre-silicon validation related to analog, digital, and mixed-signal circuits
o- Exposure to CAD tools and flows pertaining to analog silicon design and pre-si verification
o- Good understanding and knowledge in low power design techniques
o- Strong analytical, problem-solving and teamwork skills, and strong verbal and written communication skills
o- Ability to produce results in a challenging, fast-paced, and multisite, multi-group environment
o- Ability to work across functional groups and organizations
o- Understanding of the silicon development and validation cycle. Understanding of post-silicon testing/validation is a plus
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